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Ordering number : EN4991A
CMOS LSI
LC74784, 74784M
On-Screen Display Controller LSI for VCR Products
Preliminary Overview
The LC74784 and LC74784M are on-screen display CMOS LSIs that display characters and patterns on a TV screen under microprocessor control. The LC74784 and LC74784M display up to 12 lines of 24 characters, each in a 12 x 18 dot matrix.
Package Dimensions
unit: mm 3067-DIP24S
[LC74784]
Features
* Display structure: 12 lines x 24 characters (up to 288 characters) * Character structure: 12 (horizontal) x 18 (vertical) dots * Character sizes: Three size settings each in the vertical and horizontal directions * Character set: 256 characters * Display start position: 64 position settings each in the vertical and horizontal directions * Blinking: In individual character units * Blinking types: Two types with periods of about 0.5 and 1.0 second * Blanking: Whole font area blanking (12 x 18 dots) * Background colors: 8 colors (in internal synchronization mode): 4fSC (NTSC/PAL/PAL-M/ PAL-N) Background colors: 4 colors (in internal synchronization mode): 2fSC (NTSC) Background colors: 1 color (blue) (in internal synchronization mode): 2fSC (PAL/PAL-M/PAL-N) * External control input: 8-bit serial input format * Built-in sync separator circuit * Character blanked data output * Video output: Compound NTSC, PAL, PAL-N and PAL-M output
SANYO: DIP24S
unit: mm 3045B-MFP24
[LC74784M]
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
92595HA/63095TH (OT) No. 4991-1/15
LC74784, 74784M Pin Functions
Pin No. 1 2 3 4 Symbol VSS1 XtalIN XtalOUT CTRL1 Ground Crystal oscillator connection Crystal oscillator input switching Function Description Ground connection (digital system ground) Used to connect the crystal oscillator and capacitor used to generate the internal synchronization signal, or to input an external clock (2fsc or 4fsc). Switches between external clock input mode and crystal oscillator mode. Low = crystal oscillator mode, high = external clock mode Outputs the blank signal (the OR of the character and border signals). (Outputs a composite sync signal when MOD0 is high.) Outputs the crystal oscillator clock during reset (when the RST pin is low), but can be set up to not output this signal by microprocessor command. Connections for the coil and capacitor that form the oscillator that generates the character output dot clock. Outputs the character signal. (Functions as the external synchronization signal discrimination signal output pin when MOD0 is high, and outputs the state of the judgment as to whether the external synchronization signal is present or not. Outputs a high level when the synchronization signal is present.) Outputs the dot clock (LC oscillator) during reset, but can be set up to not output this signal by microprocessor command. Serial data input enable input. Serial data input is enabled when low. A pull-up resistor is built in (hysteresis input). Serial data input clock input. A pull-up resistor is built in (hysteresis input). Serial data input. A pull-up resistor is built in (hysteresis input). Composite video signal level adjustment power supply pin (analog system power supply). Composite video signal output Must be either connected to ground or left open. Video signal input Video signal input Power supply Sync separator circuit input Sync separator circuit bias voltage Composite sync signal output Vertical synchronization signal input SEPIN input control Reset input Power supply (+5 V) Composite video signal input SECAM chrominance signal input Power supply (+5 V: digital system power supply) Video signal input for the built-in sync separator circuit (Used for either horizontal synchronization signal or composite sync signal input when the built-in sync separator circuit is not used.) Built-in sync separator circuit bias voltage monitor pin Built-in sync separator circuit composite sync signal output. (When MOD1 is high, outputs a high level during internal synchronization and a low level during external synchronization.) (Outputs the SYNIN input signal when the internal sync separator circuit is not used.) Inputs a vertical synchronization signal created by integrating the SEPOUT pin output signal. An integrator must be attached at the SEPOUT pin. This pin must be tied to VDD1 if unused. Controls whether or not the VSYNC signal is input to the SEPIN input. Low = VSYNC input, high = VSYNC not input. System reset input. A pull-up resistor is built in (hysteresis input). Power supply (+5 V: digital system power supply)
5 6 7
BLANK OSCIN OSCOUT
Blanking output
LC oscillator connection
8
CHARA
Character output
9 10 11 12 13 14 15 16 17 18 19 20
CS SCLK SIN VDD2 CVOUT NC CVIN CVCR VDD1 SYNIN SEPC SEPOUT SEPIN CTRL3 RST VDD1
Enable input Clock input Data input Power supply Video signal output
21 22 23 24
No. 4991-2/15
LC74784, 74784M Pin Assignment
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg VDD1 and VDD2 pins All pins BLANK, CHARA and SEPOUT pins Ta = 25C Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 350 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 RPU VIN1 Composite video input voltage VIN2 VIN3 Input voltage VIN4 FOSC1 FOSC1 FOSC1 FOSC1 Oscillator frequency FOSC1 FOSC1 FOSC1 FOSC1 FOSC2 VDD1 pin VDD2 pin RST, CS, SIN and SCLK pins CTRL1, CTRL3 and SEPIN pins RST, CS, SIN and SCLK pins CTRL1, CTRL3 and SEPIN pins RST, CS, SIN and SCLK pins, applies to pins set by options. CVIN pin: VDD1 = 5 V SYNIN pin: VDD1 = 5 V CVCR pin: VDD1 = 5 V XtalIN pin (in external clock input mode), fin = 2fsc or 4fsc: VDD1 = 5 V XtalIN and XtalOUT oscillator pins (2fsc: NTSC) XtalIN and XtalOUT oscillator pins (4fsc: NTSC) XtalIN and XtalOUT oscillator pins (2fsc: PAL) XtalIN and XtalOUT oscillator pins (4fsc: PAL) XtalIN and XtalOUT oscillator pins (2fsc: PAL-M) XtalIN and XtalOUT oscillator pins (4fsc: PAL-M) XtalIN and XtalOUT oscillator pins (2fsc: PAL-N) XtalIN and XtalOUT oscillator pins (4fsc: PAL-N) OSCIN and OSCOUT oscillator pins (LC oscillator) 5 0.10 7.159 14.318 8.867 17.734 7.151 14.302 7.164 14.328 10 Conditions min 4.5 4.5 0.8 VDD1 0.7 VDD1 VSS - 0.3 VSS - 0.3 25 50 2.0 2.0 2.0 5.0 2.5 typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1 + 0.3 VDD1 + 0.3 0.2 VDD1 0.3 VDD1 90 Unit V V V V V V k Vp-p Vp-p Vp-p Vp-p MHz MHz MHz MHz MHz MHz MHz MHz MHz
Input high level voltage
Input low level voltage Pull-up resistance
Note: If the XtalIN pin is used in clock input mode, be sure to prevent input noise from becoming a problem.
No. 4991-3/15
LC74784, 74784M Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5 V unless otherwise specified
Parameter Input off leakage current Output off leakage current Output high level voltage Output low level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 IIH IIL Operating current drain IDD1 IDD2 Sync level VSN VPD VCBL VCBH VRSL VRSH VBK0 VBK1 VCHA CVIN pin CVOUT pin BLANK, CHARA and SEPOUT pins: VDD1 = 4.5 V, IOH = -1.0 mA BLANK, CHARA and SEPOUT pins: VDD1 = 4.5 V, IOH = 1.0 mA RST, CS, SIN, SCLK, CTRL1, CTRL3 and SEPIN pins: VIN = VDD1 CTRL1, CTRL3 and OSCIN pins: VIN = VSS1 VDD1 pin; all outputs: open, Xtal: 7.159 MHz, LC: 8 MHz VDD2 pin: VDD2 = 5 V CVOUT pin CVOUT pin CVOUT pin CVOUT pin CVOUT pin CVOUT pin CVOUT pin CVOUT pin CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V VDD1 = 5.0 V, VDD2 = 5.0 V VDD1 = 5.0 V, VDD2 = 5.0 V VDD1 = 5.0 V, VDD2 = 5.0 V VDD1 = 5.0 V, VDD2 = 5.0 V VDD1 = 5.0 V, VDD2 = 5.0 V VDD1 = 5.0 V, VDD2 = 5.0 V VDD1 = 5.0 V, VDD2 = 5.0 V VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 0.70 0.91 1.31 1.53 1.00 1.21 1.63 1.84 1.47 1.68 1.99 2.19 1.42 1.63 1.99 2.19 2.58 2.78 0.82 1.03 1.43 1.65 1.12 1.33 1.75 1.96 1.59 1.80 2.11 2.31 1.54 1.75 2.11 2.31 2.70 2.90 -1 15 20 0.94 1.15 1.55 1.77 1.24 1.45 1.87 2.08 1.71 1.92 2.23 2.43 1.66 1.87 2.23 2.43 2.82 3.02 3.5 1.0 1 Conditions min typ max 1 1 Unit A A V V A A mA mA V V V V V V V V V V V V V V V V V V
Input current
Pedestal level
Color burst low level
Color burst high level
Background color low level
Background color high level
Border level 0
Border level 1
Character level Note: 1. When the sync level is 0.8 V. 2. When the sync level is 1.0 V.
Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 0.5 V
Parameter Minimum input pulse width Symbol tW (SCLK) tW (CS) tSU (CS) tSU (SIN) th (CS) th (SIN) tword twt SCLK pin CS pin (the period when CS is high) CS pin SIN pin CS pin SIN pin 8-bit data write time RAM data write time Conditions min 200 1 200 200 2 200 4.2 1 typ max Unit ns s ns ns s ns s s
Data setup time
Data hold time
One word write time
No. 4991-4/15
LC74784, 74784M Serial Data Input Timing
No. 4991-5/15
LC74784, 74784M System Block Diagram
No. 4991-6/15
LC74784, 74784M Display Control Commands The display control commands have a serial input format with 8-bit units. A command consists of a command identifier code in the first byte and data in the second and subsequent bytes. There are eight commands as listed below. x z ~ COMMAND0: Display memory (VRAM) write address setup command COMMAND1: Display character data write command COMMAND2: Vertical display start position and vertical character size setup command COMMAND3: Horizontal display start position and horizontal character size setup command COMMAND4: Display control setup command COMMAND5: Display control setup command COMMAND6: Synchronization signal detection setup command COMMAND7: Display control setup command
Display Control Command Table
First byte Command COMMAND0 (Set write address) COMMAND1 (Write character) COMMAND2 (Set vertical display start position and vertical character size) COMMAND3 (Set horizontal display start position and horizontal character size) COMMAND4 (Display control) COMMAND5 (Display control) COMMAND6 (Synchronization signal detection) COMMAND7 (Display control) Command identification code 7 1 1 6 0 0 5 0 0 4 0 1 3 V3 0 2 V2 0 Data 1 V1 0 0 V0 at 7 0 c7 6 0 c6 5 0 c5 4 H4 c4 Second byte Data 3 H3 c3 2 H2 c2 1 H1 c1 0 H0 c0
1
0
1
0
VS 21 HS 21 TST MOD NP 1
VS 20 HS 20 RAM ERS NP 0
VS 11 HS 11 OSC STP NON DIS LIN EX 0
VS 10 HS 10 SYS RST INT MUT PD 0
0
FS
VP 5 HP 5 BLK 1 HLF INT RN 1 CIN CTL
VP 4 HP 4 BLK 0 BCL RN 0 VNP SEL
VP 3 HP 3 BK 1 CB SN 3 VSP SEL
VP 2 HP 2 BK 0 PH 2 SN 2 MSK ERS
VP 1 HP 1 RV PH 1 SN 1 MSK SEL
VP 0 HP 0 DSP ON PH 0 SN 0 EGL
1
0
1
1
0
LC
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
0 0 0 0
BLK 2 0 RN 2 CIN SEL
MOD MOD 1 0 EX 1 PD 1
Once written, the command identifier code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74784/M locks into the display character data write mode, and another first byte cannot be written. When a high level is input to the CS pin, the LC74784/M is set to COMMAND0 (display memory write address setup mode).
No. 4991-7/15
LC74784, 74784M x COMMAND0 (Display memory write address setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- V3 State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory address (0 to B hexadecimal) Command 0 identification code Set the display memory write address. Function Note
2
V2
1
V1
0
V0
Second byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- H4 State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory address (0 to 17 hexadecimal) Function Second byte identification bit Note
3
H3
2
H2
1
H1
0
H0
Note: The register states are all set to zero when the LC74784/M is reset with the RST pin.
COMMAND1 (Display character data write setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- -- -- at State 1 0 0 1 0 0 0 0 1 Character attribute off Character attribute on Command 1 identification code Set up display character data write. Function Note When this command is input, the LC74784/M locks into the display character data write mode until the CS pin goes high.
No. 4991-8/15
LC74784, 74784M Second byte
Register content DA0 to DA7 7 Register name c7 State 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character code (00 to FF hexadecimal) Function Note
6
c6
5
c5
4
c4
3
c3
2
c2
1
c1
0
c0
Note: The register states are all set to zero when the LC74784/M is reset with the RST pin.
z COMMAND2 (Vertical display start position and vertical character size setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- VS21 State 1 0 1 0 0 1 0 1 0 1 0 1 VS11 0 1 VS21 0 1 VS10 VS20 0 1H per dot 3H per dot 0 1H per dot 3H per dot 1 2H per dot 1H per dot 1 2H per dot 1H per dot First line vertical character size Second line vertical character size Command 2 identification code Set the vertical display start position and vertical character size. Function Note
2
VS20
1
VS11
0
VS10
No. 4991-9/15
LC74784, 74784M Second byte
Register content DA0 to DA7 7 6 Register name -- FS VP5 (MSB) VP4 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. Function Second byte identification bit Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc If VS is the vertical display start position then: VS = H x (2 2nVPn)
n=0 5
Note
5
4
H: the horizontal synchronization pulse period
3
VP3
2
VP2
1
VP1 VP0 (LSB)
0
Note: The register states are all set to zero when the LC74784/M is reset with the RST pin.
COMMAND3 (Horizontal display start position and horizontal character size setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- HS21 State 1 0 1 1 0 1 0 1 0 1 0 1 HS11 0 1 HS21 0 1 HS10 HS20 0 1 Tc per dot 3 Tc per dot 0 1 Tc per dot 3 Tc per dot 1 2 Tc per dot 1 Tc per dot 1 2 Tc per dot 1 Tc per dot First line horizontal character size Second line horizontal character size Command 3 identification code Set the horizontal display start position and horizontal character size. Function Note
2
HS20
1
HS11
0
HS10
Second byte
Register content DA0 to DA7 7 6 Register name -- LC HP5 (MSB) HP4 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Second byte identification bit An LC oscillator is used for the dot clock. A crystal oscillator is used for the dot clock. If HS is the horizontal start position then: HS = Tc x (2 2nHPn)
n=0 5
Note
Selects the dot clock used in horizontal character display.
5
4
Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. The horizontal display start position is set by the six bits HP5 to HP0. The weight of bit 1 is 2Tc.
3
HP3
2
HP2
1
HP1 HP0 (LSB)
0
Note: The register states are all set to zero when the LC74784/M is reset with the RST pin.
No. 4991-10/15
LC74784, 74784M COMMAND4 (Display control setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- TSTMOD State 1 1 0 0 0 1 0 2 RAMERS 1 1 OSCSTP 0 1 0 1 Reset all registers and turn the display off. Erase display RAM (set to FF hexadecimal) Do not stop the crystal oscillator and LC oscillator circuits. Stop the crystal oscillator and LC oscillator circuits. Normal operating mode Test mode This bit must be zero. Command 4 identification code Display control Function Note
The RAM erase operation requires about 500 s (It is executed in the DSPOFF state.) Valid when character display is off in external synchronization mode. Reset occurs when the CS pin is low, and the reset is cleared when CS goes high.
0
SYSRST
Second byte
Register content DA0 to DA7 7 6 Register name -- BLK2 State 0 0 1 0 BLK1 BLK0 1 0 1 0 1 0 2 BK0 1 1 RV 0 1 0 DSPON 1 Blinking on Reverse (character reversing) off Reverse (character reversing) on Character display off Character display on BLK1 0 1 Function Second byte identification bit Character display block Video display block BLK0 0 Blanking off Border size 1 Character size Full character size Switches the blinking period. When blinking is specified for reversed characters, the blinking will be between normal character and reversed character display. Changes the blanking size. Full character size specification Note
5
4
3
BK1
Blinking period: about 0.5 s Blinking period: about 1.0 s Blinking off
0
Note: The register states are all set to zero when the LC74784/M is reset with the RST pin.
No. 4991-11/15
LC74784, 74784M COMMAND5 (Display control setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- NP1 State 1 1 0 1 0 1 0 1 0 1 0 1 Interlaced Non-interlaced External synchronization Internal synchronization NP1 0 1 NP0 0 NTSC PAL 1 PAL-M PAL-N Switches between interlaced and noninterlaced displays Switches between external and internal synchronization Command 5 identification code Display control Function Note
Switches between NTSC, PAL, PAL-M and PAL-N
2
NP0
1
NON
0
INT
Second byte
Register content DA0 to DA7 7 6 5 Register name -- -- HLFINT State 0 0 0 1 0 1 0 1 0 2 PH2 1 0 1 PH1 1 0 0 PH0 1 Normal mode Half internal synchronization mode Background color present No background color (only the background level is set) Outputs a color burst signal. Stops color burst signal output. Phase 2 0 0 0 0 1 1 1 1 Phase 1 0 0 1 1 0 0 1 1 Phase 0 0 1 0 1 0 1 0 1 Background color (phase) NTSC /2* In phase* 3/2* * 3/4 /4 7/4 5/4 PAL /2 In phase - + /2 3/4 /4 - + /4 - + 3/4 *: When 2fsc NTSC is used Only valid when BCL is high. Sample background color phase diagram for PAL mode color burst Only valid with internal synchronization. Function Second byte identification bit Note
4 3
BCL CB
Note: The register states are all set to zero when the LC74784/M is reset with the RST pin.
No. 4991-12/15
LC74784, 74784M ~ COMMAND6 (Synchronization signal detection setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- MOD1 State 1 1 1 0 0 1 0 2 MOD0 1 1 DISLIN 0 1 0 1 Sync separator circuit signal High level output during internal synchronization Pin 5: Blank signal Pin 8: Character signal Pin 5: Composite synchronization signal Pin 8: External synchronization signal discrimination output signal 12 lines 10 lines Normal output CVIN is cut and CVOUT is fixed at the pedestal level. Switches the SEPOUT (pin 19) output Command 6 identification code Synchronization signal control settings Function Note
Switches the BLANK (pin 5) and CHARA (pin 8) outputs
Switches the number of display lines.
0
MUT
Switches CVOUT
Second byte
Register content DA0 to DA7 7 6 Register name -- RN2 State 0 0 1 0 RN1 RN0 1 0 1 0 1 0 1 0 1 0 SN0 1 SN3 SN2 SN1 SN0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 Number of times HSYNC detected Not detected 32 times 64 times 128 times 256 times External synchronization signal detection control Signal present to absent transition recognition Setting for the sampling period when SYNC can not be detected consecutively in the horizontal synchronization signal period (1H). RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Number of times HSYNC detected 0 times 4 times 8 times 16 times Function Second byte identification bit External synchronization signal detection control Signal absent to present transition recognition Setting for the sampling period when SYNC can be detected consecutively in the horizontal synchronization signal period (1H). Note
5
4
3
SN3
2
SN2
1
SN1
0
Note: The register states are all set to zero when the LC74784/M is reset with the RST pin.
COMMAND7 (Display control setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- EX1 State 1 1 1 1 0 1 0 1 0 1 0 1 MODE1 setting output PORT DATA1 setting output The output is set low. The output is set high. MODE0 setting output PORT DATA0 setting output The output is set low. The output is set high. Switches the BLANK (pin 5) output Switches the SEPOUT (pin 19) output Command 7 identification code Display control setup Function Note
2
PD1
1
EX0
0
PD0
No. 4991-13/15
LC74784, 74784M Second byte
Register content DA0 to DA7 7 6 Register name -- CINSEL State 0 0 1 0 1 0 4 VNPSEL 1 3 VSPSEL 0 1 0 1 0 1 0 1 V rising edge detection VSEP: about 8.9 s (for NTSC) VSEP: about 17.8 s (for NTSC) Mask valid Mask invalid 3H (for NTSC) 20H (for NTSC) Border level 0 only (VBK0) Border level has two stages (VBK0, VBK1) Function Second byte identification bit Blank (the OR of the character and the border) signal area Video signal display area CVCR: Off CVCR: On V falling edge detection Switches the CVCR on signal CVCR on/off setting Switches V acquisition polarity when internal V separation is used in external mode. Note
5
CINCTL
Switches the internal V separation time.
2
MSKERS
HSYNC and VSYNC mask release
1
MSKSEL
Switches the VSYNC mask. Switches the border level (Only valid for BLK0 = 0 and BLK1 = 1)
0
EGL
Note: The register states are all set to zero when the LC74784/M is reset with the RST pin.
Display Screen Structure The display consists of 24 characters x 12 rows. The maximum number of displayed character is 288. The maximum number of characters is reduced to less than 288 when the character size is enlarged. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses)
No. 4991-14/15
LC74784, 74784M Composite Video Signal Output Level (internally generated level)
CVOUT output level waveform (VDD2 = 5.00 V)
Output level VCHA: Character VBK1: Border VRSH: Background color high VCBH: Color burst high VRSL: Background color low VBK0: Border VPD: VSN: Pedestal VCBL: Color burst low Sync VDD2 = 5.00 V Output voltage [V] 2.70 2.11 2.11 1.75 1.59 1.54 1.43 1.12 0.82 Output voltage [V] 2.90 2.31 2.31 1.96 1.80 1.75 1.65 1.33 1.03
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of Feburuary, 1997. Specifications and information herein are subject to change without notice. PS No. 4991-15/15
Caption P.5
1. Serial to parallel converter 2.
Character output dot clock generator
19. Line control counter 20. Synchronization signal generator 21.
Blinking and inversion control register
22.
Blinking and inversion control circuit
3.
Sync separator
23. 4. 8-bit latch + command decoder 5. 6. 24.
Sync discriminator
Character output control Background control Video output control
Display control register 25. RAM write address counter 26. 26. Decoder Decoder Display RAM Font ROM Shift register
Composite synchronizati on signal separator control
7.
Horizontal character size register
8. Horizontal size counter 9.
Vertical character size register
27. 28. 29.
10. Vertical size counter 11. 12.
Horizontal display position register
P.8
10. Character display area
Timing generator
P.13
1. 2. 24 Characters 12 Rows
13. Horizontal dot counter 14.
Horizontal display position detector
15. Character control counter 16.
Vertical display position register
17. Vertical dot counter 18.
Vertical display position detector
NEW P.3
DIP24S, MFP24
P.6/15
Composite sync signal separator control
15/15
VPD

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